Therefore, phase growth in the copper-tin system in the presence of various metal barriers at the interface is evaluated. Further, the scaling of microjoints in such 3-dimensional chip-stacks is proposed by means of kinetic control. This results in a homogenized and rigid joint with excellent mechanical properties, suitable for step by step stack building. By solid-liquid interdiffusion (isothermal solidification) the solder filled connection zone is entirely transformed into intermetallic compounds. The process of stacking employs a solder based bonding method, which results in a rigid and thermally stable connection. It is shown how an electrical interconnect path from the top to the bottom of a mechanically sound chip stack can be realized.

As an example application, the two key elements, the micro vias and the micro joints are formed on bare silicon substrate. The micro vias are processed from the backside and therefore do not impose routing restrictions on the front side of the circuit. This thesis treats the technologigal aspects of a novel 3D-integration concept, which is based on processes that follow the sequence: wafer thinning, via processing, chip stacking. It allows a smaller ciruit footprint by chip-stacking and can combine a variety of technologies. A comparison of wafer-level 3D integration with system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.ДЈD-integration, or vertical chip integration, is a technology that aims to shorten the interconnect path between integrated circuits and to increase the interconnect density by using through-chip micro vias. Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS SOI devices and circuits indicate the viability of the process flow. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs.

Flow free bridges pack 6x6 level 3